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january 2011 doc id 18198 rev 1 1/52 AN3308 application note lis3dh: mems digital output motion sensor ultra low-power high performance 3-axis ?nano? accelerometer introduction this document describes the low-voltage 3-axis digital output linear mems accelerometer provided in an lga package. the lis3dh is an ultra low-power high performance 3-axis linear accelerometer belonging to the ?nano? family, with a digital i 2 c/spi serial interface standard output. the device features ultra low-power operational modes that allow advanced power saving and smart sleep-to-wake-up and return-to-sleep functions. the lis3dh has dynamic user selectable full scales of 2g/4g/8g/16g and it is capable of measuring accelerations with output data rates from 1 hz to 5 khz. the device may be configured to generate interrupt signals by an independent inertial wake- up/free-fall event as well as by the position of the device itself. thresholds and timing of the interrupt generator are programmable by the end user on the fly. automatic programmable sleep-to-wake-up and return-to-sleep functions are also available for enhanced power saving. the lis3dh has an integrated 32-level first in first out (fifo) buffer allowing the user to store data for host processor intervention reduction. the lis3dh is available in a small thin plasti c land grid array package (lga) and it is guaranteed to operate over an extended temperature range from -40 c to +85 c. the ultra small size and weight of the smd package make it an ideal choice for handheld portable applications such as cell phones and pdas, or any other application where reduced package size and weight are required. www.st.com
contents AN3308 2/52 doc id 18198 rev 1 contents 1 registers table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 switch mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 reading acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.2 using the data-ready (dry) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.3 using the block data update (bdu) feature . . . . . . . . . . . . . . . . . . . . . . 13 3.2 understanding acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 big-little endian selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.3 example of acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 high-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.3 autoreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 interrupt pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 inertial interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 free-fall and wake-up interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3.1 inertial wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3.2 hp filter bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AN3308 contents doc id 18198 rev 1 3/52 6.3.3 using the hp filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 free-fall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 6d/4d orientation detec tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 6d orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 4d direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 click and double click recognitio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 single click . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.2 double click . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.3.1 tap_cfg (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.3.2 tap_src (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3.3 tap_ths (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3.4 time_limit (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3.5 time_latency (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3.6 time window (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.3.7 ctrl_reg3 [interrupt ctrl register] (22h) . . . . . . . . . . . . . . . . . . . . 35 8.4 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4.1 playing with tap_timelimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.4.2 playing with tap_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.4.3 playing with tap_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 first in first out (fifo) buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 fifo description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 fifo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.1 control register 5 (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.2 fifo control register (0x2e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.3 fifo source register (0x2f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.3 fifo modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.4 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4 watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5 retrieve data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 contents AN3308 4/52 doc id 18198 rev 1 10 auxiliary adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 AN3308 list of tables doc id 18198 rev 1 5/52 list of tables table 1. registers table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. power consumption (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. switch mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. output data registers content vs. acceleration (fs = 2 g) . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. low power mode - high-pass filter cut-off frequency [hz]. . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. reference mode lsb value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. ctrl_reg6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. ctrl_reg6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 14. interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 15. duration lsb value in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 16. threshold lsb value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 17. int1_src register in 6d position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18. tap_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 19. tap_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 20. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 21. tap_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22. tap_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 23. tap_ths register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 24. tap_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 25. time_limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 26. time_limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 27. time_latency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 28. time_latency description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 29. time_window description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 30. time_latency description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 31. ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 32. ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 33. fifo buffer full representation (32nd sample set stored). . . . . . . . . . . . . . . . . . . . . . . . . 39 table 34. fifo overrun representation (33rd sample set stored and 1st sample discarded) . . . . . 40 table 35. fifo enable bit in ctrl_reg5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 36. fifo_ctrl_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 37. fifo_src_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 38. fifo_src_reg behavior assuming fth[4:0] = 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 39. ctrl_reg3 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 40. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 list of figures AN3308 6/52 doc id 18198 rev 1 list of figures figure 1. data ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. high-pass filter connections block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. hp_filter_reset readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 4. reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. autoreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. interrupt signals and interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. free-fall, wake-up interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. ff_wu_cfg high and low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. inertial wake-up interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. free-fall interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. zh, zl, yh, yl, xh, and xl behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 12. 6d movement vs. 6d position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. 6d recognized positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. single click event with non latched interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. single and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16. double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17. short timelimit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18. long timelimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19. short latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 20. long latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 21. short window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 22. long window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 23. fifo_en connection block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 figure 24. fifo mode behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 25. stream mode fast reading behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 26. stream mode slow reading behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 figure 27. stream mode slow reading zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 28. stream-to-fifo mode: interrupt not latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 29. stream-to-fifo mode: interrupt latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 figure 30. watermark behavior - fth[4:0] = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 31. fifo reading diagram - fth[4:0] = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 AN3308 registers table doc id 18198 rev 1 7/52 1 registers table table 1. registers table register name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 status_reg_aux 07h 321or 3or 2or 1or 321da 3da 2da 1da out_adc1_l 08h a1d7 a1d6 a1d5 a1d4 a1d3 a1d2 a1d1 a1d0 out_adc1_h 09h a1d15 a1d14 a1d13 a1d12 a1d11 a1d10 a1d9 a1d8 out_adc2_l 0ah a2d7 a2d6 a2d5 a2d4 a2d3 a2d2 a2d1 a2d0 out_adc2_h 0bh a2d15 a2d14 a2d13 a2d12 a2d11 a2d10 a2d9 a2d8 out_adc3_l 0ch a3d7 a3d6 a3d5 a3d4 a3d3 a3d2 a3d1 a3d0 out_adc3_h 0dh 3a3d15 c2 a3d13 a3d12 a3d11 a3d10 a3d9 a3d8 int_counter_reg0ehc7 c6c5c4c3c2 c1 c0 who_am_i 0fh0 01100 1 1 temp_cfg_reg 1fh adc_pd temp_en 0 0 0 0 0 0 ctrl_reg1 20h odr3 odr2 odr1 odr0 lpen zen yen xen ctrl_reg2 21h hpm1 hpm0 hpcf2 hpcf1 fds hpclick hpis2 hpis1 ctrl_reg3 22h i1_click i1_aoi1 0 i1_drdy1 i1_drdy2 i1_wtm i1_overrun - ctrl_reg4 23h bdu ble fs1 fs0 hr st1 st0 sim ctrl_reg5 24h boot fifo_en - - lir_int1 d4d_int1 0 0 ctrl_reg6 25h i2_clicken i2_int1 0 boot_i1 0 - h_lactive - reference 26h ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 status_reg2 27h zyxor zor yor xor zyxda zda yda xda out_x_l 28h xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 out_x_h 29h xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 out_y_l 2ah yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 out_y_h 2bh yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 registers table AN3308 8/52 doc id 18198 rev 1 out_z_l 2ch zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 out_z_h 2dh zd15 zd14 zd13 zd12 zd11 zd10 zd9 zd8 fifo_ctrl_reg 2e fm1 fm0 tr fth4 fth3 fth2 fth1 fth0 fifo_src_reg 2f wtm ovrn_fif o - fss4 fss3 fss2 fss1 fss0 int1_cfg 30h aoi 6d zhie zlie yhie ylie xhie xlie int1_src 31h - ia zh zl yh yl xh xl int1_ths 32h 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 int1_duration 33h 0 d6 d5 d4 d3 d2 d1 d0 click_cfg 38h - zd zs yd ys xd xs click_src 39h - ia dclick sclick sign z y x click_ths 3ah - ths6 ths5 ths4 ths3 ths2 ths1 ths0 time_limit 3bh - tli6 tli5 tli4 tli3 tli2 tli1 tli0 time_latency 3ch tla7 tla6 tla5 tla4 tla3 tla2 tla1 tla0 time_window 3dh tw7 tw6 tw5 tw4 tw3 tw2 tw1 tw0 act_ths 3eh - aths6 aths5 aths4 aths3 aths2 aths1 aths0 inact_dur 3fh adur7 adur6 adur5 adur4 adur3 adur2 adur1 adur0 table 1. registers table (continued) register name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AN3308 operating modes doc id 18198 rev 1 9/52 2 operating modes the lis3dh provides three different operating modes, respectively reported as power-down mode, normal mode, and low power mode. while normal mode guarantees higher resolution, low power mode further reduces the current consumption. after power supply is applied, the lis3dh performs a 5 ms boot procedure to load the trimming parameter. after the boot is completed, the device is automatically configured in power-down mode. referring to the lis3dh datasheet, output data rate (odr) and low power enable (lpen) bits of ctrl_reg1 and hr bits of ctrl_reg4 are used to select the operating modes (power-down mode, normal mode and low power mode) and output data rate ( ta b l e 2 and ta bl e 3 ). ta bl e 4 shows the typical values of the power consumption for the different operating modes. table 2. operating mode selection operating mode ctrl_reg1[3] (lpen bit) ctrl_reg4[3] (hr bit) bw [hz] turn-on time [ms] low power mode 1 0 odr/2 1 normal mode 0 1 odr/9 7/odr table 3. data rate configuration odr3 odr2 odr1 odr0 power mode selection 0000 power-down mode 0001 normal/low power mode (1 hz) 0010 normal/low power mode (10 hz) 0011 normal/low power mode (25 hz) 0100 normal/low power mode (50 hz) 0101 normal/low power mode (100 hz) 0110 normal/low power mode (200 hz) 0111 normal/low power mode (400 hz) 1000 low power mode (1.5 khz) 1001normal (1. 250 khz)/low power mode (5 khz) table 4. power consumption ( a) odr(hz) normal mode ( a) low power mode ( a) power-down 0.4 0.4 12 2 operating modes AN3308 10/52 doc id 18198 rev 1 2.1 power-down mode when the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. digital interfaces (i 2 c and spi) are still active to allow communication with the device. the configuration registers content is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode. 2.2 normal mode in normal mode, data are generated at the data rate (odr) selected through the dr bits and for the axis enabled through zen, yen, and xen bits of ctrl_reg1. data generated for a disabled axis is 00h. data interrupt generation is active and configured through the int1_cfg register. 2.3 low power mode while normal mode guarantees higher resolution, low power mode further reduces the current consumption. in low power mode, data are generated at the data rate (odr) selected through the dr bits and for the axis enabled through the zen, yen, and xen bits of ctrl_reg1. data generated for a disabled axis is 00h. data interrupt generation is active and configured through the int1_cfg register. 10 4 3 25 6 4 50 11 6 100 20 10 200 38 18 400 73 36 1250 185 - 1600 - 99 5000 - 184 table 4. power consumption ( a) (continued) odr(hz) normal mode ( a) low power mode ( a) AN3308 operating modes doc id 18198 rev 1 11/52 2.4 switch mode timing switch mode time is shown in ta bl e 1 . table 5. switch mode timing starting mode target mode turn on time - typ (ms) power-down low power 2/odr power-down normal 7/odr normal power-down 0 low power power-down 0 low power normal 7/odr normal low power 2/odr startup sequence AN3308 12/52 doc id 18198 rev 1 3 startup sequence once the device is powered-up, it automatically downloads the calibration coefficients from the embedded flash to the internal registers. when the boot procedure is completed, i.e. after approximately 5 milliseconds, the device automatically enters power-down mode. to turn on the device and gather acceleration data, it is necessary to select one of the operating modes through ctrl_reg1 and to enable at least one of the axes. the following general purpose sequence can be used to configure the device: 3.1 reading acceleration data 3.1.1 using the status register the device is provided with a status_reg which should be polled to check when a new set of data is available. the reading procedure should be the following: 1. write ctrl_reg1 2. write ctrl_reg2 3. write ctrl_reg3 4. write ctrl_reg4 5. write ctrl_reg5 6. write ctrl_reg6 7. write reference 8. write int1_ths 9. write int1_dur 10. write int1_cfg 11. write ctrl_reg5 1. read status_reg 2. if status_reg(3) = 0 then go to 1 3. if status_reg(7) = 1 then some data have been overwritten 4. read outx_l 5. read outx_h 6. read outy_l 7. read outy_h 8. read outz_l 9. read outz_h 10. data processing 11. go to 1 AN3308 startup sequence doc id 18198 rev 1 13/52 the check performed at step 3 allows to understand whether the reading rate is adequate compared to the data production rate. in case one or more acceleration samples have been overwritten by new data, because of a too slow reading rate, the zyxor bit of status_reg is set to 1. the overrun bits are automatically cleared when all the data present inside the device have been read and new data have not been produced in the meantime. 3.1.2 using the dat a-ready (dry) signal the device may be configured to have one hw signal to determinate when a new set of measurement data is available for reading. this signal is represented by the xyzda bit of status_reg. the signal can be driven to int1 pin by setting the i1_drdy1 bit of ctrl_reg3 to 1 and its polarity set to active-low or active-high through the h_lactive bit of ctrl_reg6. the data-ready signal rises to 1 when a new set of acceleration data has been generated and it is available for reading.the interrupt is reset when the higher part of the data of all the enabled channels has been read (29h, 2bh, 2dh). figure 1. data ready signal 3.1.3 using the block dat a update (bdu) feature if the reading of the acceleration data is particularly slow and cannot be synchronized (or it is not required) with either the xyzda bit present inside the status_reg or with the rdy signal, it is strongly recommended to set the bdu (block data update) bit in ctrl_reg4 to 1. this feature avoids the reading of values (most significant and least significant parts of the acceleration data) related to different samples. in particular, when the bdu is activated, the data registers related to each channel always contain the most recent acceleration data produced by the device, but, in case the reading of a given pair (i.e. out_x_h and out_x_l, out_y_h and out-y_l, out_z_h and out_z_l) is initiated, the refresh for that pair is blocked until both msb and lsb parts of the data are read. note: bdu only guarantees that out_x(y, z)_l and out_x(x,z)_h have been sampled at the same moment. for example, if the reading speed is too low, it may read x and y sampled at t1 and z sampled at t2. " . w 2 $ 9 $ ! 4 ! 2 % ! $ . e l p m a 3 l e c c ! . e l p m a 3 l e c c ! ! 4 ! $ , % # # ! 8 9 : 8 9 : startup sequence AN3308 14/52 doc id 18198 rev 1 3.2 understanding acceleration data the measured acceleration data are sent to outx_h, outx_l, outy_h, outy_l, outz_h, and outz_l registers. these registers contain, respectively, the most significant part and the least significant part of the acceleration signals acting on the x, y, and z axes. the complete acceleration data for the x (y, z) channel is given by the concatenation outx_h & outx_l (outy_h & outy_l, outz_h & outz_l) and it is expressed as a 2?s complement number. 3.2.1 data alignment acceleration data are represented as 16-bit numbers and are left justified. 3.2.2 big-little endian selection the lis3dh allows to swap the content of the lower and the upper part of the acceleration registers (i.e. outx_h with outx_l), to be compliant with both little-endian and big-endian data representations. ?little endian? means that the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address. (the little end comes first). this mode corresponds to bit ble in ctrl_reg4 reset to 0 (default configuration). on the contrary, ?big endian? means that the high-order byte of the number is stored in memory at the lowest address, and the low-order byte at the highest address. 3.2.3 example of acceleration data ta bl e 6 provides a few basic examples of the data that is read in the data-registers when the device is subject to a given acceleration. the values listed in the table are given under the hypothesis of perfect device calibration (i.e. no offset, no gain error,....) and practically show the effect of the ble bit. table 6. output data registers content vs. acceleration (fs = 2 g ) acceleration values ble = 0 ble = 1 register address 28h 29h 28h 29h 0 g 00h 00h 00h 00h 350 mg e0h 15h 15h e0h 1 g 00h 04h 04h 00h -350 mg 20h eah eah 20h -1g 00h c0h c0h 00h AN3308 high-pass filter doc id 18198 rev 1 15/52 4 high-pass filter the lis3dh provides an embedd ed high-pass filtering capabilit y to easily delete the dc component of the measured acceleration. as shown in figure 2 , through fds, hpen1, and hpen2 bits of ctrl_reg2 configuration, it is possible to independently apply the filter on the output data and/or on the interrupts data. this means that it is possible, i.e., to get filtered data while interrupt generation works on unfiltered data. figure 2. high-pass filter connections block diagram 4.1 filter configuration referring to ta bl e 7 , two operating modes are possible for the high-pass filter: the bandwidth of the high-pass filter depends on the selected odr and on the settings of hpcfx bits of ctrl_reg2. the high-pass filter cut-off frequencies (f t ) are shown in ta bl e 8 . ! - v + 3 ) l o w h u , q w h u u x s w & |